This website is a learning hub for VLSI physical design and ASIC backend implementation. It organizes core concepts in the order that engineers usually encounter them in a real design flow, including logic synthesis, physical design inputs, floorplanning, placement, clock tree synthesis, routing, static timing analysis, power analysis, IR drop analysis, ECO, and physical verification. The goal is to make difficult physical design topics easier to understand without losing the technical vocabulary used in industry tools and signoff reviews.
Each page is designed to act as a quick reference for students and practicing engineers who want to review fundamentals, prepare for interviews, or connect one implementation stage to the next. The site also includes project and blog sections that can be expanded with case studies, flow notes, and timing closure examples to show how physical design decisions affect power, performance, area, congestion, and manufacturability.
If you are learning the RTL-to-GDSII implementation flow, start from synthesis and move through floorplanning, placement, CTS, routing, STA, and signoff pages in sequence for the best continuity.
This structure is especially useful for newcomers to semiconductor backend design because it keeps the learning path aligned with the real implementation sequence used in ASIC projects. You can use the site as a study roadmap for interviews, course revision, or self-paced learning in VLSI physical design and signoff fundamentals.