CCS Modeling

Introduction

In VLSI design, cell models are abstract representations of standard logic gates (like inverters or NAND gates). Static Timing Analysis (STA) tools use these models to predict chip performance. As technology shrinks below 90nm (submicron), physical effects that were once minor become dominant, requiring more advanced models. The Composite Current Source (CCS) model is the modern standard for this task.

From NLDM to CCS: The Need for a Better Model

The industry standard before CCS was the Non-Linear Delay Model (NLDM). NLDM uses lookup tables to find a cell's delay based on input signal speed (slew) and the total capacitance of the output wire (load). This approach has critical failures in modern designs:

• Inaccuracy with Resistance: NLDM assumes wires are purely capacitive. Modern wires have significant resistance, which NLDM cannot model, leading to errors of 10-18%.
• Miller Effect Blindness: It uses a single, fixed value for a gate's input capacitance. In reality, this capacitance changes dynamically during switching (the Miller effect), a major factor NLDM misses.
• Waveform Distortion: It simplifies signals into simple ramps, ignoring distortions from crosstalk that affect the timing of subsequent gates.

To solve these issues, the industry shifted to the Composite Current Source (CCS) model. CCS represents a fundamental change: instead of providing a delay value, it provides the full output current waveform. The STA tool uses this current to calculate the resulting voltage waveform on any connected wire network, accurately predicting the final delay.

The CCS Driver Model

The core of CCS is modeling the output of a gate as a time-varying, nonlinear current source. The Liberty file contains a lookup table that stores different output current waveforms, indexed by the input signal's slew and the total output load capacitance. Because a current source model is independent of the load's topology, it remains accurate even when driving complex, resistive-capacitive (RC) wires.

The CCS Receiver Model

An accurate receiver model must account for the Miller effect, where the effective input capacitance of an inverting gate increases during its transition. CCS solves this by modeling the input capacitance with two distinct values:

• C1: The capacitance used for the part of the transition before the 50% voltage threshold.
• C2: The capacitance used for the part of the transition after the 50% threshold, capturing the peak of the Miller effect.

This two-stage capacitance model allows the STA tool to accurately calculate the total charge needed to switch the node, resulting in precise delay and slew calculations.

Liberty File Syntax for CCS

CCS models are defined in Liberty (.lib) text files. Below are simplified examples of the syntax for the driver and receiver models.

Driver Model Syntax

The driver's current waveform data is stored in an output_current_rise or output_current_fall group. The vector block contains the actual current values for a specific input slew (index_1) and output load (index_2) over time (index_3).

timing() {
    output_current_rise() {
        vector (CCS) {
            reference_time: 0.05;
            index_1(0.2);             /* Input slew value */
            index_2(0.091);           /* Output capacitance value */
            index_3(1.1, 1.2, 1.3);   /* Time points (ps) */
            values("-0.1, -0.2, -0.3"); /* Current values (mA) */
        }
    }
}

Receiver Model Syntax

The receiver's two-capacitor model is defined with receiver_capacitance1_rise and receiver_capacitance2_rise attributes. These point to a lookup table where the capacitance values are indexed by input slew and output load.

timing() {
    related_pin: "A";
    receiver_capacitance1_rise (TEMPLATE_NAME) {
        values("0.0076, 0.0080, 0.0081, \\
                0.0077, 0.0080, 0.0081"); /* C1 values */
    }
    receiver_capacitance2_rise (TEMPLATE_NAME) {
        values("0.0093, 0.0087, 0.0081, \\
                0.0095, 0.0088, 0.0082"); /* C2 values */
    }
}

CCS for Noise Analysis (CCSN)

Beyond timing, CCS also has an extension for signal integrity analysis called CCS Noise (CCSN). It is used to analyze crosstalk, where a switching signal (aggressor) induces an unwanted voltage spike (glitch) on a quiet neighboring wire (victim).

The CCSN model includes:

• DC Current Tables: Define the cell's ability to reject an incoming noise glitch (noise immunity).
• Propagated Noise Tables: Characterize how an input glitch is reshaped as it passes through the cell, determining if it will be amplified or attenuated.

Models can be arc-based (for simple gates, modeling full propagation) or pin-based (for complex cells like flip-flops, modeling only the input and output stages).

pin(D) {
    /* Pin-based model for a flip-flop input */
    ccsn_first_stage() {
        is_needed: true;
        stage_type: both;
        dc_current (DC_TEMPLATE) { ... }
        propagated_noise_low (PROP_TEMPLATE) { ... }
    }
}

Advanced CCSN for Sub-10nm

For technologies at 10nm and below, even standard CCSN can be inaccurate for complex cells. Advanced CCSN enhances the model by breaking a cell down into its fundamental Channel-Connected Blocks (CCBs), which are groups of physically connected transistors.

This allows the model to describe a noise propagation path through a specific sequence of internal CCBs, providing much higher fidelity for complex internal logic. The Liberty syntax is extended with attributes like propagating_ccb to define this path.

timing () {
    related_pin: "A";
    /* Defines the specific internal path for this timing arc */
    propagating_ccb ("CCB_A_NAND1", "CCB_Z_INV");
}

Conclusion: The CCS Paradigm Shift

The Problem: Why Old Models Fail

In older semiconductor technologies (like 90nm and above), the behavior of transistors and wires was predictable enough to be simplified. We could use linear models like Thévenin's theorem, which represents a driving gate as a simple voltage source with a fixed internal resistance (R_on). The load it was driving could be modeled as a single, fixed capacitor (C_L).

This allowed for a simple, one-step delay calculation: τ_p ≈ 0.69 ⋅ R_on ⋅ C_L

However, in modern Deep Submicron (DSM) nodes (like 7nm), this linear approximation completely breaks down. The internal "resistance" and "capacitance" are no longer fixed values; they become highly non-linear and dynamic due to two main physical effects:

1. Velocity Saturation: In the short channel of a DSM transistor, electrons reach a maximum speed limit. This means the drive current (I_ds) is no longer proportional to the voltage, so the effective resistance is not constant during a switch.
2. The Miller Effect: The capacitance between the input and output of the receiving gate creates a feedback loop. This makes the effective load capacitance dynamically increase during the middle of a transition.

The Solution: The Composite Current Source (CCS) Model

CCS solves this problem by abandoning the flawed R and C model entirely. Instead, it models the components as they behave in the real world: as complex, non-linear current sources.

1. Modeling the Driver

The driving gate is modeled as a dynamic current source whose output, I_driver, is a function of both the input slew and the instantaneous output voltage (V_out). This is stored in a 2D lookup table pre-characterized with thousands of accurate SPICE simulations.

I_driver(t) = f(Input Slew, V_out(t))

This inherently captures the non-linear current behavior caused by velocity saturation.

2. Modeling the Load

The receiving gate is modeled with two components:

• A static capacitor (C_static) for the fixed part of the load.
• A dynamic current source (I_Miller) that explicitly models the extra current drawn due to the Miller effect during the transition.

I_load(t) = C_static * dV_out/dt + I_Miller(t)

The Calculation: A Step-by-Step Simulation

A Static Timing Analysis (STA) tool uses these current-based models to perform a precise, iterative simulation. It no longer uses a simple one-step formula.

1. Select Driver Model: Based on the input signal's slew rate, the STA tool selects the appropriate current model (a "row" in the 2D table) for the driver.
2. Iterate Over Time: For each tiny time-step (Δt), the tool solves Kirchhoff's Current Law for the output node: I_driver(t) - I_load(t) = 0
3. Find Slew Rate: It rearranges this to find the instantaneous output slew rate: dV_out/dt = (I_driver(t) - I_Miller(t)) / C_static
4. Update Voltage: It uses the slew rate to calculate the new output voltage for the next time-step.
5. Repeat: The tool repeats this loop, constantly looking up the new I_driver based on the new V_out, until the output voltage crosses the 50% threshold.

The total time elapsed during this simulation is the propagation delay. This dynamic, iterative method is far more accurate because it directly simulates the real, non-linear physics of the circuit.