Works Cited

A consolidated list of references from all articles.

From "Advanced Synthesis"

  • Synthesis Methodology & Netlist Qualification - Design And Reuse, accessed September 13, 2025, https://www.design-reuse.com/article/61358-synthesis-methodology-netlist-qualification/
  • logic_synthesis_html_1.pdf
  • LEF, DEF & LIB - SignOff Semiconductors, accessed September 13, 2025, https://signoffsemiconductors.com/lef-def-lib/
  • Contents in the LIB, LEF and DEF files - Learn VLSI, accessed September 13, 2025, https://learnvlsi.com/pd/liblef-and-def/222/
  • Inputs for Physical Design | VLSI - logicmadness.com, accessed September 13, 2025, https://logicmadness.com/inputs-for-physical-design/
  • Tutorial on Cadence Genus Synthesis Solution, accessed September 13, 2025, http://public2.yuantsy.com/Test/ECE201A/Genus_Tutorial.pdf
  • ECE 5745 Tutorial 5: Synopsys/Cadence ASIC Tools - GitHub Pages, accessed September 13, 2025, https://cornell-ece5745.github.io/ece5745-tut5-asic-tools/
  • What is difference between logical synthesis and physical synthesis? - VLSI Interview Community - Quora, accessed September 13, 2025, https://vlsiqaforstudents.quora.com/What-is-difference-between-logical-synthesis-and-physical-synthesis
  • SYNTHESIS - VLSI TALKS, accessed September 13, 2025, https://vlsitalks.com/physical-design/synthesis/
  • Introduction to Netlist (.v), LEF, and DEF Files - Wix.com, accessed September 13, 2025, https://vorasaumil.wixsite.com/pdinsight/post/introduction-to-netlist-lef-def-files
  • (PDF) Optimization of Physically-Aware Synthesis for Digital Implementation Flow, accessed September 13, 2025, https://www.researchgate.net/publication/324526833_Optimization_of_Physically-Aware_Synthesis_for_Digital_Implementation_Flow

From "CMOS Fundamentals"

  • 0072460539cmos.pdf
  • Band diagram - Wikipedia, accessed September 11, 2025, https://en.wikipedia.org/wiki/Band_diagram
  • Energy Diagram of PN junction & Depletion Region - Automation Forum, accessed September 11, 2025, https://automationforum.co/energy-diagram-of-pn-junction-depletion-region/
  • energy band structure of open circuited pn junction - WordPress.com, accessed September 11, 2025, https://ashwinjs.files.wordpress.com/2019/02/energy-band.pdf
  • PN and Metal–Semiconductor Junctions, accessed September 11, 2025, https://www.chu.berkeley.edu/wp-content/uploads/2020/01/Chenming-Hu_ch4-1.pdf
  • Biasing of P-N Junctions - HyperPhysics, accessed September 11, 2025, http://hyperphysics.phy-astr.gsu.edu/hbase/Solids/pnjun2.html

From "Clock Tree Synthesis"

  • a partitionable clock distribution system for sequential visi circuits, accessed September 11, 2025, https://www.hajim.rochester.edu/ece/sites/friedman/papers/ISCAS_86.pdf
  • Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs, accessed September 11, 2025, https://www.mdpi.com/2079-9292/12/20/4340
  • Clock Tree Synthesis - SignOff Semiconductors, accessed September 11, 2025, https://signoffsemiconductors.com/clock-tree-synthesis-1/
  • CTS (CLOCK TREE SYNTHESIS) - VLSI TALKS, accessed September 11, 2025, https://vlsitalks.com/physical-design/cts/
  • cts_html.pdf

From "Floorplanning"

  • Floorplanning in Physical Design. In the intricate world of VLSI... | by VLSIPD | Medium, accessed September 13, 2025, https://medium.com/@vlsipd4/floorplanning-in-physical-design-052e4fe2bb66
  • Floorplanning in VLSI Design: A Comprehensive Guide - Medium, accessed September 13, 2025, https://medium.com/@ifrit057/floorplanning-in-vlsi-design-a-comprehensive-guide-85a12c097ea9
  • Floorplan (microelectronics) - Wikipedia, accessed September 13, 2025, https://en.wikipedia.org/wiki/Floorplan_(microelectronics)
  • Physical design (electronics) - Wikipedia, accessed September 13, 2025, https://en.wikipedia.org/wiki/Physical_design_(electronics)

From "Logic Synthesis"

  • logic_synthesis_html_1.pdf
  • What is Synthesis in VLSI? - Maven Silicon, accessed September 11, 2025, https://www.maven-silicon.com/blog/what-is-synthesis-in-vlsi/
  • VLSI Synthesis: Complete Guide from Basics to Advanced | Theory & Hands-On Practical Marathon, accessed September 11, 2025, https://www.youtube.com/watch?v=gLqr8t-RRIA
  • Topic 3 in PD: Synthesis Flow Overview: Optimizing RTL to Netlist - YouTube, accessed September 11, 2025, https://www.youtube.com/watch?v=9OQUBt9HLXo

From "PD Inputs"

  • Inputs of physical design | ODP - SlideShare, accessed September 11, 2025, https://www.slideshare.net/slideshow/inputs-of-physical-design/79931343
  • Standard-Cell Libraries 101: What They Are & How They Shape Your VLSI Design, accessed September 11, 2025, https://vlsifacts.com/standard%E2%80%91cell-libraries-101-what-they-are-how-they-shape-your-vlsi-design/
  • Physical design (electronics) - Wikipedia, accessed September 11, 2025, https://en.wikipedia.org/wiki/Physical_design_(electronics)
  • pd_inputs_html.pdf

From "Placement"

  1. www.scribd.com, accessed September 17, 2025, https://www.scribd.com/document/461537047/Placement#:~:text=It%20defines%20placement%20as%20the, more%20signals%20than%20available%20tracks.
  2. Placement in VLSI Design: A Detailed Overview | 2025 | New Tricks - logicmadness.com, accessed September 17, 2025, https://logicmadness.com/placement-in-vlsi/
  3. 1.define Placement in Physical Design? | PDF | Digital Technology - Scribd, accessed September 17, 2025, https://www.scribd.com/document/461537047/Placement
  4. Placement - VLSI Begin, accessed September 17, 2025, http://vlsibegin.blogspot.com/p/placement.html
  5. placement_html.pdf
← Previous Projects