PD Verification
Signoff checks that protect tapeout quality.
What Gets Verified
PD verification ensures the layout matches the netlist and meets manufacturing rules. It also validates timing, noise, and power integrity.
The goal is to catch issues that could cause silicon failures or yield loss.
Core Signoff Checks
DRC ensures geometric rules and spacing are respected.
LVS confirms connectivity matches the schematic or netlist.
STA validates setup and hold timing under signoff corners.
IR drop and EM analysis confirm PDN robustness.
Best Practices
Run signoff checks incrementally, not only at the end.
Track waivers and justify them with data.
Keep your signoff decks and constraints versioned.