Static Timing Analysis

What STA Does

STA evaluates all timing paths in a design using library models and constraints. It reports setup, hold, and recovery/removal checks without requiring simulation vectors.

Key outputs include worst negative slack (WNS), total negative slack (TNS), and path-based diagnostics.

Core Concepts

Setup checks ensure data arrives before the clock edge.

Hold checks ensure data remains stable after the clock edge.

Clock uncertainty, OCV derates, and RC parasitics add realism to signoff.

Practical Checklist

Fix setup with faster cells, buffering, or path restructuring.

Fix hold with delay insertion or clock path tuning.

Validate constraints and clock definitions before deep optimization.

Timing Analysis in VLSI

Ensuring that a digital design operates correctly at its target clock frequency is the goal of timing analysis. In a synchronous system, all operations are coordinated by a clock signal, and data must be successfully transmitted and captured between sequential elements (like flip-flops) within a single clock cycle. Static Timing Analysis (STA) is the industry-standard methodology for verifying this.

7.1 Fundamental Timing Concepts for Sequential Elements

The behavior of a flip-flop is governed by strict timing requirements relative to the active clock edge.

• Setup Time (T_su): This is the minimum amount of time that the data input (D) of a flip-flop must be stable before the arrival of the active clock edge. If the data changes within this setup window, the flip-flop may enter a metastable state and capture an incorrect value.
• Hold Time (T_h): This is the minimum amount of time that the data input (D) must remain stable after the arrival of the active clock edge. If the data changes within this hold window, the new value might corrupt the data that was supposed to be captured.
• Clock-to-Q Delay (T_cq): This is the propagation delay of the flip-flop itself-the time it takes for the output (Q) to reflect the captured data value after the active clock edge.

7.2 The Clock Signal: Skew and Jitter

The clock signal is assumed to be a perfect, periodic signal in ideal analysis, but in reality, it is subject to variations that impact timing.

• Clock Skew: This is the difference in the arrival time of the same clock edge at different flip-flops across the chip. It is a spatial variation caused by differences in the physical path (wire length and buffer delays) of the clock distribution network. A positive skew between a launching and capturing flip-flop helps with setup timing but hurts hold timing, while a negative skew does the opposite.
• Clock Jitter: This is the deviation of a clock edge from its ideal position in time. It is a temporal variation caused by noise in the clock generation circuitry (e.g., PLLs) and power supply noise. Jitter effectively reduces the available time within a clock cycle and must be budgeted for in timing analysis.
• Clock Uncertainty: In STA, a timing margin called clock uncertainty is used to model the combined effects of jitter and other unpredictable variations, effectively tightening the timing requirements to ensure a robust design.

7.3 Introduction to Static Timing Analysis (STA)

STA is a method of verifying the timing of a design by analyzing all possible paths without performing circuit simulation. It is a cornerstone of modern digital design verification due to its speed and completeness.

• Key Concepts:
  • Timing Paths: STA decomposes the circuit into a collection of timing paths. Each path starts at a startpoint (an input port of the chip or the clock pin of a flip-flop) and ends at an endpoint (an output port or the data input pin of a flip-flop).
  • Arrival Time (AT): The time it takes for a signal to propagate from its startpoint to any given point along a path.
  • Required Arrival Time (RAT): The latest time a signal can arrive at a point without causing a timing violation.
  • Slack: The difference between the RAT and the AT. A positive slack indicates that timing is met with some margin, while a negative slack indicates a timing violation that must be fixed.
• Setup and Hold Checks: STA performs two fundamental checks for every timing path between sequential elements.
  • Setup Check (Maximum Delay Check): This check ensures that the data path is not too slow. Data launched from a flip-flop at one clock edge must arrive at the next flip-flop before its setup time window for the next clock edge. The analysis considers the longest possible delay through the combinational logic and the shortest possible delay for the clock path to the capturing flop (worst-case scenario). The setup slack is calculated as:
    Slacksetup = (Clock Period + Tskew) - (Tcq + Tlogic,max + Tsu)
  • Hold Check (Minimum Delay Check): This check ensures that the data path is not too fast. New data launched from a flip-flop must not arrive at the next flip-flop so quickly that it violates the hold time of the data captured on the previous clock edge. The analysis considers the shortest possible delay through the combinational logic and the longest possible delay for the clock path to the capturing flop. The hold slack is calculated as:
    Slackhold = (Tcq + Tlogic,min) - (Tskew + Th)

A fundamental tension exists between these two checks. The most common way to fix a setup violation is to make the logic path faster (e.g., by upsizing gates or using lower-V_th cells). However, making the path faster increases the risk of creating a hold violation. Conversely, the standard way to fix a hold violation is to make the logic path slower by adding delay (e.g., inserting buffers). This, in turn, can introduce a setup violation. For this reason, timing closure is a complex, iterative optimization process performed by EDA tools, typically involving fixing setup violations first at the worst-case (slow) process corner, followed by fixing hold violations at the best-case (fast) process corner.

Related Topics

• Delay Models
• STA Numericals
• Clock Tree Synthesis

Static Timing Analysis in the Physical Design Flow

Static Timing Analysis is not an isolated step in backend implementation. STA is the backbone of digital signoff because it evaluates setup and hold timing across process, voltage, temperature, and mode combinations without relying on a single simulation waveform. In a practical ASIC flow, engineers revisit this topic at least twice: once to prevent problems early, and again after optimization when the design context changes because of timing fixes, buffering, or routing decisions.

When using this page for learning or interview preparation, separate the topic into inputs, tool actions, and outputs. Inputs define what data must be clean before you start. Tool actions describe what the engine is optimizing. Outputs show whether the run is actually improving design quality. The most useful reviews combine those three views instead of memorizing a short definition.

Practical Checklist

Use this quick checklist while studying or debugging static timing analysis. It helps turn theory into repeatable engineering practice and also improves project documentation quality.

• Confirm clocks, generated clocks, and uncertainties are defined correctly
• Check input and output delays against real interface assumptions
• Separate setup and hold closure strategies to avoid conflicting fixes
• Review derates, OCV settings, and corner coverage for signoff readiness
• Group violations by root cause before launching broad optimization

Track the result of each change with measurable data instead of intuition alone. Track worst slack, total negative slack, violating endpoints, path groups, and correlation between implementation and signoff STA tools. Keeping a small log of assumptions, changes, and outcomes will make this topic easier to revise later and easier to explain in interviews or design reviews.