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Samson Hruday Chinta

University of Minnesota, Twin Cities

Contact & Links

Email: chint078@umn.edu

LinkedIn: linkedin.com/in/chintasamsonhruday

Skills

  • Languages: Python, Tcl, C++
  • Logic Design: SystemVerilog, Verilog, LT Spice, CMOS VLSI Design, Sizing, Dynamic Logic, Static Timing Analysis
  • Tools: Synopsys, ICC2, Fusion Compiler, Verdi, Design Compiler, Primetime, Cadence Innovus, Virtuoso
  • Coursework: VLSI Design I & II, VLSI Lab, Computer Architecture, Solid State Physics, VLSI Design Automation

Work Experience

CPU Physical Design Automation/Methodology Intern

Intel Corporation | Austin, TX | May 2025 – Dec 2025

  • Developed, tested and supported tools, APR flows and methodologies for building partitions using EDA tools.
  • Integrated new procedures into existing EDA tools, adding new features and improving script runtime by 30%.
  • Enabled APR flows for Intel 18A & TSMC N2P process nodes across multiple projects in regression tools.
  • Created a rapid-turnaround design case to test APR flows in Cadence (Innovus, Genus) and Synopsys tools (FC).
  • Collaborated with cross-functional teams to create comprehensive UPF, SAIF and DFT data for the test case.

Graduate Teaching Assistant

University of Minnesota | Twin Cities, MN | Aug 2024 – May 2025

  • Assisted students in EE3006 and Fundamentals of Electrical Engineering with lab work involving oscilloscopes, power supplies, signal generators, and power amplifiers, guiding them through circuit design and analysis.

Deputy Engineer

Bharat Electronics Limited | Hyderabad, India | Dec 2022 – July 2024

  • Engineered the FPGA solution for a military-grade Software-Defined Radio (SDR), enabling secure communications in the L-band (1.2-1.6 GHz) with a peak transmission power of 30 dBm.
  • Designed a 5G MMwave antenna that resonates at 27Ghz with a gain of 14 dBi; increased gain by 3 dBi using Metamaterials without compromising on Bandwidth.
  • Integrated high-speed ADCs & DACs, Power Amplifiers, and IQ modulation/demodulation for RF signal processing.

Projects

Pipelined CNN Convolution & Pooling Accelerator

Tools: VCS Verdi, DC Compiler, Primetime | Jan 2025 – May 2025

  • Architected and optimized a CNN accelerator in Verilog for the TSMC 16nm node, advancing the design from a 4 to 5-stage pipeline to boost maximum frequency by 45% to 1.82 GHz.
  • Executed logic synthesis and Static Timing Analysis (STA) using Synopsys Design Compiler, achieving timing closure on all critical reg2reg paths at 1.82 GHz with a 0.54 ns delay and zero slack.
  • Conducted post-synthesis PPA analysis at 0.8V, reporting a total power of 30.02 mW (via PrimeTime PX) and a 9,408.86 µm² cell area, with combinational logic consuming 93% of the power.
  • Verified functional correctness by running pre-synthesis & post-synthesis simulations for 65,536 test vectors in VCS.

Structural CDC Verification Engine for Gate-Level Netlists

Tools: Python, Design Compiler | Jan 2025 – May 2025

  • Deployed a Python-based structural analysis tool to parse Synopsys gate-level netlists and verify CDC integrity.
  • Implemented a custom graph-based engine with a Depth-First Search (DFS) algorithm to automatically detect all CDC paths, classify synchronizers, and identify unsafe crossings.
  • Integrated advanced checks for glitch-risk and multi-bit reconvergence hazards to reliable CDC signoff.

RTL-to-GDSII Implementation of an 8x8 2D DCT Processor

Tools: Primetime, DC Compiler, ICC2 | Aug 2024 – Dec 2024

  • Designed RTL in Verilog, incorporating an FSM and a counter to synchronize control signals and data flow across submodules, achieving 833 MHz clock speed and 17 mW power consumption.
  • Performed synthesis using Synopsys Design Compiler, optimizing area (17,000 µm²), power, and timing, achieving 30% clock gating efficiency, and incorporated scan chains achieving 99.89% fault coverage.
  • Reduced PPA with floorplanning, power planning, placement, CTS, and routing (PnR) in Synopsys ICC2, resolving IR drop issues and optimizing pin placement for minimal congestion.
  • Optimized placement and CTS, achieving 100 ps clock skew, reducing routing congestion from 5% to 0.1%.
  • Implemented global and detailed routing, and completed signoff analysis using PrimeTime.

4-to-1 Integrate-and-Fire Neuron Design for High Speed Applications

Tools: TSMC 16nm PDK | Oct 2024 – Dec 2024

  • Formulated a high-speed 4-to-1 Integrate-and-Fire (IF) neuron, achieving improved latency and power efficiency.
  • Utilized custom Assessed 1-bit adders, Dynamic D flip-flops, and logic gates using 16nm TSMC PDK.
  • Analyzed propagation delay of a combinational circuit, optimized it to 61ps, and combined with a C2MOS flip-flop, achieving a 15GHz operating frequency.
  • Efficiently determined 1-bit firing condition (F) to integrated output (z), optimizing signal integrity and speed.

CMOS Inverter Analysis

Tools: Cadence Virtuoso, Hspice, TSMC 16nm PDK | Nov 2024 – Dec 2024

  • Simulated CMOS inverter circuits in Cadence Virtuoso and Hspice using 16nm TSMC PDK.
  • Evaluated propagation delay, power dissipation, and switching characteristics for 16nm FinFET design.
  • Assessed 2nd order metrics like leakage current, focusing on advanced low-power performance.
  • Skills: SPICE · Cadence Spectre · Cadence Virtuoso · Integrated Circuits (IC) · Application-Specific Integrated Circuits (ASIC)
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