PD Verification
Signoff checks that protect tapeout quality.
What Gets Verified
PD verification ensures the layout matches the netlist and meets manufacturing rules. It also validates timing, noise, and power integrity.
The goal is to catch issues that could cause silicon failures or yield loss.
Core Signoff Checks
DRC ensures geometric rules and spacing are respected.
LVS confirms connectivity matches the schematic or netlist.
STA validates setup and hold timing under signoff corners.
IR drop and EM analysis confirm PDN robustness.
Best Practices
Run signoff checks incrementally, not only at the end.
Track waivers and justify them with data.
Keep your signoff decks and constraints versioned.
Related Topics
Physical Design Verification in the Physical Design Flow
Physical Design Verification is not an isolated step in backend implementation. Physical verification ensures the implemented layout matches manufacturing and connectivity requirements before tapeout, making it a core signoff gate rather than a final checklist item. In a practical ASIC flow, engineers revisit this topic at least twice: once to prevent problems early, and again after optimization when the design context changes because of timing fixes, buffering, or routing decisions.
When using this page for learning or interview preparation, separate the topic into inputs, tool actions, and outputs. Inputs define what data must be clean before you start. Tool actions describe what the engine is optimizing. Outputs show whether the run is actually improving design quality. The most useful reviews combine those three views instead of memorizing a short definition.
Practical Checklist
Use this quick checklist while studying or debugging physical design verification. It helps turn theory into repeatable engineering practice and also improves project documentation quality.
- Run DRC, LVS, antenna, and density checks with the correct rule deck version
- Classify violations into systematic versus isolated issues before fixing
- Confirm that ECO changes do not reopen previously closed verification errors
- Coordinate with routing and layout updates to fix root causes efficiently
- Preserve clean signoff reports for review and tapeout documentation
Track the result of each change with measurable data instead of intuition alone. Track DRC count, LVS status, antenna results, density compliance, and turnaround time for each verification iteration. Keeping a small log of assumptions, changes, and outcomes will make this topic easier to revise later and easier to explain in interviews or design reviews.