Delay Models in VLSI | VLSI Physical Design Hub

Overview

Timing engines use pre-characterized models to estimate cell delay and output slew. These models are essential for fast, accurate static timing analysis across large designs.

The accuracy of delay modeling depends on input slew, output load, and interconnect effects.

Key Models

NLDM uses lookup tables indexed by input slew and output capacitance. It is fast and widely supported.

CCS models output current waveforms and captures non-linear effects better at advanced nodes.

Interconnect delay adds RC effects and can dominate total path delay in deep submicron designs.

Practical Guidance

Use CCS where available for better accuracy on aggressive nodes.

Keep slew within library limits to avoid pessimistic or invalid timing.

Use real extracted parasitics during late-stage signoff.

Delay Models in the Physical Design Flow

Delay Models is not an isolated step in backend implementation. Accurate delay modeling is essential because synthesis, STA, and optimization engines all depend on timing estimates to make decisions. In a practical ASIC flow, engineers revisit this topic at least twice: once to prevent problems early, and again after optimization when the design context changes because of timing fixes, buffering, or routing decisions.

When using this page for learning or interview preparation, separate the topic into inputs, tool actions, and outputs. Inputs define what data must be clean before you start. Tool actions describe what the engine is optimizing. Outputs show whether the run is actually improving design quality. The most useful reviews combine those three views instead of memorizing a short definition.

Practical Checklist

Use this quick checklist while studying or debugging delay models. It helps turn theory into repeatable engineering practice and also improves project documentation quality.

Know when a flow is using ideal interconnect assumptions versus extracted RC data
Understand the difference between NLDM and CCS timing model behavior
Check transition and load ranges to avoid extrapolation errors in libraries
Validate that constraints and corners match the libraries used in analysis
Use signoff correlation as the final reference for model confidence

Track the result of each change with measurable data instead of intuition alone. Compare delay and slew predictions against extracted parasitics and signoff reports to understand model limits at each stage. Keeping a small log of assumptions, changes, and outcomes will make this topic easier to revise later and easier to explain in interviews or design reviews.

Delay Models